This example uses RTL hw acceleration in the streaming path. The module is located between the sensor interface and the dma. It consists of a 32-Bit master and 32-Bit slave axi-stream interface for sensor pixel data and a 32-Bit axi-lite control interface for register access.
After processing the image is sent out via gige - server.
This example uses no hw acceleration. But it uses the same infrastructure like other hw accelerated examples. The main processing consists of a simple c-code scaler for horizontal and vertical rescaling.
After processing the image is sent out via gige - server.