iam provides 64-bit processor scalability while combining real-time control with soft and hard engines for graphics and video. With the NET SDK and GigE Vision toolboxes shown below customers can start comfortably to build their unique vision system with iam. The open system architecture of iam enables customers to use both CPU and FPGA processing resources for their application.
Introducing the NET Open Camera Concept for iam
In section you will find a varius software example application where we briefly described how to optimize the application code by using hardware acceleration by synthesizing a FPGA co-processor into the programmable logic of the camera.
Video: The NET Open Camera Concept (OCC)
See all Video Tutorial Session .
Example Repository
The iam_apps example repository is structured into the steps below.
Set up a Virtual Host System for cross-compiling including FPGA synthesis.
Check out example repository net-gmbh/iam_apps
git clone https://bitbucket.org/net-gmbh/iam_apps.gitBuild the iam software platform project.
Check out and chose one of our example projects including iAMGigEServer or build one of hundreds Xilinx Vitis vision library examples from the repositories below.
Deploy your software to camera using
app2cam.shscript.
The figure below illustrates the described steps above and the following table summarizes the example projects.
Example Name | Compiling | Discription |
|---|---|---|
sw_scaler_synview | cross | This example uses no hardware acceleration. After processing the image is sent out via GigE Server. |
ccode_synview | cross | The example code_synview uses HLS hw acceleration written in C-code. The main processing method can be selected among following choices:
After processing the image is sent out via GigE Server. |
remap_synview | cross | The example remap_synview uses the hardware acceleration function xf::cv::remap from the Vitis vision library. After processing, the image is sent out via GigE Server. |
dice_synview | cross | The example dice_synview demonstrates dice cube detection and dots counting for each cube. It uses multiple xfOpenCV functions. |
rtl_threshold_synview | cross | This example uses RTL hardware acceleration written in Verilog. After processing, the image is sent out via GigE Server. |
strm_rtl_threshold_synview | cross | This example uses RTL hardware acceleration in the streaming path. After processing, the image is sent out via GigE Server. |
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Background and Strategy
Hardware Acceleration: Optimizing Effects
The processing power of iam can be improved by FPGA optimization effects such as pipelining, parallelization, co-processing, and quantization.
Hardware Acceleration: Kernels Types
The figure below shows different methodes of writing acceleration kernels for iam. Most of the different ways are covered by a software example in the net-gmbh/iam_apps repository.
Introduction to Cross Compiling
Cross-compilation is the act of compiling code for one computer system (often known as the target) on a different system, called the host.
Xilinx Vitis IDE TM
Introducing Vitis IDE TM
The Xilinx Vitis unified software platform enables the development of embedded software and accelerated applications on heterogeneous Xilinx platforms including FPGAs, SoCs, and Versal ACAPs. It provides a unified programming model for accelerating your iam applications.
Develop and deploy hardware accelerated application
Work on an application level
Comfortable eclipse editor
Several desing examples from NET net-gmbh/iam_apps
Even more from Xilinx Vitis Vision Library
Profiling and live debugging on iam
More information can be found at Vitis Unified Software Platform
Include Examples Repository to Vitis IDE
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🔍 References
👥 contact NET