This example uses no hardware acceleration. But it uses the same infrastructure like other hardware accelerated examples. The main processing consists of a simple C-code scaler for horizontal and vertical rescaling.
After processing the image is sent out via GigE Server.
This example uses HLS hw acceleration with the xfOpenCV function xf::cv::boxfilter in the streaming path.The module is located after the sensor interface and before the dma. The AXI-Stream data width convertion will be done by either axiStrm_wInc/axiStrm_wDec (HLS-implementation) or axiStrm_wInc_rtl/axiStrm_wDec_rtl (RTL-implementation).
strm_rtl_threshold_synview
cross
This example uses RTL hardware acceleration in the streaming path. The module is located between sensor interface and dma. It consists of a 32-bit master and 32-bit slave axi-stream interface for sensor pixel data and a 32-bit axi-lite control interface for register access.
After processing, the image is sent out via GigE Server.
This example uses no hardware acceleration. But it uses the same infrastructure like other hardware accelerated examples. The main processing consists of a simple C-code scaler for horizontal and vertical rescaling.
After processing the image is sent out via GigE Server.