This example uses no hardware acceleration. But it uses the same infrastructure like other hardware accelerated examples. The main processing consists of a simple C-code scaler for horizontal and vertical rescaling.
After processing the image is sent out via GigE server.
This example uses RTL hardware acceleration in the streaming path. The module is located between sensor interface and dma. It consists of a 32-bit master and 32-bit slave axi-stream interface for sensor pixel data and a 32-bit axi-lite control interface for register access.
After processing, the image is sent out via GigE server.