iam provides 64-bit processor scalability while combining real-time control with soft and hard engines for graphics and video. With the NET SDK and GigE Vision toolboxes shown below customers can start comfortably to build their unique vision system with iam. The open system architecture of iam enables customers to use both CPU and FPGA processing resources for their application.

Introducing the NET Open Camera Concept for iam

In section you will find a varius software example application where we briefly described how to optimize the application code by using hardware acceleration by synthesizing a FPGA co-processor into the programmable logic of the camera.

Example Repository

The iam_apps example repository is structured into the steps below.

Set up a Virtual Host System for cross-compiling including FPGA synthesis.
Check out example repository net-gmbh/iam_apps
git clone https://bitbucket.org/net-gmbh/iam_apps.git
Build the iam software patform project.
Check out and chose one of our example projects including iAMGigEServer or build one of hundreds xilinx vitis vision library examples from the repositories below.
1. net-gmbh/iam_apps
2. Xilinx/Vitis_Libraries
Deploy your software to camera using app2cam.sh script.

The figure below illustrates the described steps above and the following table summarizes the example projects.

Example Name	Compiling	Discription
sw_scaler_synview	cross	This example uses no hardware acceleration. But it uses the same infrastructure like other hardware accelerated examples. The main processing consists of a simple C-code scaler for horizontal and vertical rescaling. After processing the image is sent out via GigE server.
ccode_synview	cross	The example code_synview uses HLS hw acceleration written in C-code. The main processing method can be selected among following choices: no processing simple C-code software processing a optimized C-code version with ARM NEON instructions processing with OpenCV functions Hardware accelerated processing based on a C-code source After processing the image is sent out via GigE server.
remap_synview	cross	The example remap_synview uses the hardware acceleration function xf::cv::remap from the Vitis vision library. After processing, the image is sent out via GigE server.
dice_synview	cross	The example dice_synview demonstrates dice cube detection and dots counting for each cube. It uses multiple xfOpenCV functions.
rtl_threshold_synview	cross	This example uses RTL hardware acceleration written in Verilog. After processing, the image is sent out via GigE server.
strm_rtl_threshold_synview	cross	This example uses RTL hardware acceleration in the streaming path. The module is located between sensor interface and dma. It consists of a 32-bit master and 32-bit slave axi-stream interface for sensor pixel data and a 32-bit axi-lite control interface for register access. After processing, the image is sent out via GigE server.

Background and Strategy

Hardware Acceleration: Optimizing Effects

The processing power of iam can be improved by FPGA optimization effects such as pipelining, parallelization, co-processing, and quantization.

Hardware Acceleration: Kernels Types

The figure below shows different methodes of writing acceleration kernels for iam. Most of the different ways are covered by a software example in thenet-gmbh/iam_apps repository.

Introduction to Cross Compiling

Cross-compilation is the act of compiling code for one computer system (often known as the target) on a different system, called the host.

Xilinx Vitis IDE ^TM

Introducing Vitis IDE ^TM

The Xilinx Vitis unified software platform enables the development of embedded software and accelerated applications on heterogeneous Xilinx platforms including FPGAs, SoCs, and Versal ACAPs. It provides a unified programming model for accelerating your iam applications.