iam provides 64-bit processor scalability while combining real-time control with soft and hard engines for graphics and video. With the NET SDK and GigE Vision toolboxes shown below customers can start comfortably to build their unique vision system with iam. The open system architecture of iam enables customers to use both CPU and FPGA processing resources for their application.
| Excerpt | ||||
|---|---|---|---|---|
|
Introducing the NET Open Camera Concept for iam
In section you will find a varius various software example application where we briefly described how to optimize the application code by using hardware acceleration by synthesizing a FPGA co-processor into the programmable logic of the camera.
Video: The NET Open Camera Concept (OCC)
| Confluence youtube macro video | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|
|
See all Video Tutorial Session .
Example Repository
The iam_apps example repository is structured into the steps below.
Set up a Virtual Host System for cross-compiling including FPGA synthesis.
Check out example repository net-gmbh/iam_apps
git clone https://bitbucket.org/net-gmbh/iam_apps.gitBuild the iam software
platform project.
Download latest platform source achive file (download section).Check out and chose one of our example projects including iAMGigEServeriAMGigEServer or build one of hundreds
Xilinx Vitis vision library examples from the repositories below.
Deploy your software to camera using
app2cam.shscript.
The figure below illustrates the described steps above and the following table summarizes the example projects.
Example Name
Compiling
Discription
sw_scaler_synview
cross
But it uses the same infrastructure like other hardware accelerated examples.
The main processing consists of a simple C-code scaler for horizontal and vertical rescaling.
After processing the image is sent out via GigE server.
ccode_synview | cross | The example code_synview uses HLS hw acceleration written in C-code. The main processing method can be selected among following choices:
After processing the image is sent out via GigE |
|---|
Server. | ||
remap_synview | cross | The example remap_synview uses the hardware acceleration function xf::cv::remap from the Vitis vision library. After processing, the image is sent out via GigE |
|---|
Server. |
remap_boxfilter_synview | cross | The example |
|---|
remap_boxfilter_synview uses the hw acceleration function xf::cv::remap from the Vitis vision library and the cv::remap and cv::boxfilter function from OpenCV. After processing, the image is sent out via GigE Server. | ||
rtl_threshold_synview | cross | This example uses RTL hardware acceleration written in verilog. After processing, the image is sent out via GigE Server. |
|---|---|---|
rtl_threshold_synview_dfx | cross | This example uses RTL hardware acceleration written in |
verilog. It consists of two different threshold accelerators, but only one of them can be loaded into the programmable logic. The module can be changed dynamically during running acquisition. This function is called DFX (Dynamic Function eXchange) and can help to use different accelerators that wouldn't fit together in the fpga part. After processing, the image is sent out via GigE Server. | ||
strm_boxfilter_synview | cross | This example uses HLS hardware acceleration with the xfOpenCV function xf::cv::boxfilter in the streaming path. After processing, the image is sent out via GigE |
|---|
Server. | ||
strm_rtl_threshold_synview | cross | This example uses RTL hardware acceleration in the streaming path. After processing, the image is sent out via GigE |
|---|
Server. | ||
sw_scaler_synview | cross | This example uses no hardware acceleration. After processing the image is sent out via GigE Server. |
|---|---|---|
sw_frm_buf_config_synview | cross | This example uses no hardware acceleration But it uses the same infrastructure like other hw accelerated examples. The application does no processing. The purpose of the app is to demonstrate how to configure (buffer-number, number of max. buffer delay) the input frame buffer manager. After processing the image is sent out via GigE Server. |
 |
|
Background and Strategy
Hardware Acceleration: Optimizing Effects
The processing power of iam can be improved by FPGA optimization effects such as pipelining, parallelization, co-processing , and quantization.
Hardware Acceleration: Kernels Types
The figure below shows different methodes of writing acceleration kernels for iam. Most of the different ways are covered by a software example in the net-gmbh/iam_apps repository.
Introduction to Cross Compiling
| Info |
|---|
Cross-compilation is the act of compiling code for one computer system (often known as the target) on a different system, called the host. |
Xilinx Vitis IDE TM
Introducing Vitis IDE TM
The Xilinx Vitis unified software platform enables the development of embedded software and accelerated applications on heterogeneous Xilinx platforms including FPGAs, SoCs, and Versal ACAPs. It provides a unified programming model for accelerating your iam applications.
Develop and deploy hardware accelerated application
Work on an application level
Comfortable eclipse editor
Several desing examples from NET net-gmbh/iam_apps
Even more from Xilinx Vitis Vision Library
Profiling and live debugging on iam
More information can be found at Vitis Unified Software Platform
Include Examples Repository to Vitis IDE
iam_apps/apps_gui/ |
|
🔍 References
👥 contact NET
| Insert excerpt | ||||||
|---|---|---|---|---|---|---|
|